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Madhavi, B. K.
- Design of Ultra Low Power 8 Bit Arithmetic and Logic Unit Using Subthreshold Source Coupled Logic
Abstract Views :259 |
PDF Views:3
Authors
Affiliations
1 ECE Department, CVR College of Engineering, Hyderabad, Telangana, IN
2 ECE Department, Sri Devi Engineering College, Telangana, IN
1 ECE Department, CVR College of Engineering, Hyderabad, Telangana, IN
2 ECE Department, Sri Devi Engineering College, Telangana, IN
Source
International Journal of Research in Signal Processing, Computing & Communication System Design, Vol 2, No 1-2 (2016), Pagination: 10-13Abstract
Designing ultralow power circuits with improved speed and power optimization is a challenging job in the design of a microprocessor. The main component of any processor is the ALU design. STSCL works at very low voltages, consumes less power and has promising performance. In this paper, an ultralow power ALU using STSCL technique in 45nm technology at 1V power supply using cadence virtuoso tools is presented.Keywords
STSCL, ALU, MCML.- Low Power VLSI Design with Resistive Feedback Logic
Abstract Views :213 |
PDF Views:117
Authors
Affiliations
1 ECE dept, TRR Engg. College, Hyderabad, AP, IN
2 ECE Dept., SNIST, Ghatkesar, Hyderabad, AP, IN
3 JNTU College of Engg., Kukatpally, Hyderabad, IN
1 ECE dept, TRR Engg. College, Hyderabad, AP, IN
2 ECE Dept., SNIST, Ghatkesar, Hyderabad, AP, IN
3 JNTU College of Engg., Kukatpally, Hyderabad, IN
Source
AIRCC's International Journal of Computer Science and Information Technology, Vol 2, No 1 (2010), Pagination: 96-104Abstract
These papers focus on the development of low power VLSI design methodology on system level modeling and circuit level modeling for power optimization. The developed transition optimization approach further merged with circuit level power optimization using Glitch minimization technique. A resistive feed back method is developed for the elimination of glitches in the CMOS circuitry, which result in power consumption and reducing performance of VLSI design. The optimized sequence is then processed through a 8-bit register bank modeled in CMOS level for data transfer to observe the glitch effect. Tanner EDA tool is used for the designing of the CMOS circuitry with resistive feedback mechanism for power optimization.Keywords
Low Power VLSI, Glitch Free Modeling, Resistive Feedback Logic, Stray Capacitance.- Improving Attainment of Graduate Attributes using Google Classroom
Abstract Views :163 |
PDF Views:3
Authors
Affiliations
1 Department of Computer Science and Engineering, Nalla Malla Reddy Engineering College, Hyderabad, IN
1 Department of Computer Science and Engineering, Nalla Malla Reddy Engineering College, Hyderabad, IN